IISc develops next-generation analog chipsets for AI applications

Researchers at the Indian Institute of Science (IISc) have developed a design framework for the creation of next-generation analog computing chipsets, which may operate quicker and with less power than the digital chips used in the majority of electronic gadgets.

The team has built a prototype of an analog chipset named ARYABHAT-1 using their innovative design framework (Analog Reconfigurable technologY And Bias-scalable Hardware for AI Tasks). This kind of chipset can be particularly useful for Artificial Intelligence (AI)-based applications like object or speech recognition - think Alexa or Siri - or those that call for massive parallel computing operations at high speeds.

However, the researchers added that there were several technology hurdles to overcome while designing analog chips. "Another challenge is that trading off precision and speed with power and area is not easy when it comes to analog design. In digital design, simply adding more components like logic units to the same chip can increase precision, and the power at which they operate can be adjusted without affecting the device performance," says the IISc release.

"To overcome these challenges, the team has designed a novel framework that allows the development of analog processors which scale just like digital processors. Their chipset can be reconfigured and programmed so that the same analog modules can be ported across different generations of process design and across different applications. You can synthesise the same kind of chip at either 180 nm or at 7 nm, just like digital design," says Chetan Singh Thakur, Assistant Professor, IISc.

The design framework was developed as part of IISc student Pratik Kumar's PhD work, and in collaboration with Shantanu Chakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis (WashU), USA, who also serves as WashU's McDonnell Academy ambassador to IISc. "It's good to see the theory of analog bias-scalable computing being manifested in reality and for practical applications," says Chakrabartty, who had earlier proposed bias-scalable analog circuits. Two pre-print studies that are undergoing peer review present the findings of the researchers. Additionally, they have applied for patents, and they intend to collaborate with business partners to commercialise the technology.